1. Field of the Invention
The present invention relates to a light emitting device which has an element with a luminescent material put between electrodes, a manufacturing method thereof, and an electronic appliance using the light emitting device for the display (an indication display or a displaying monitor), particularly to a light emitting device using a luminescent material by which EL (Electro Luminescence) can be obtained (hereinafter referred to as an EL material) and a manufacturing method thereof. The light emitting device according to the present invention includes an organic EL display and an OLED (Organic Light Emitting Diode).
The luminescent material that can be used in the present invention includes all of materials which emit light (phosphorescence and/or fluorescence) through singlet excitation, triplet excitation, or both.
2. Description of the Related Art
Recently, there has been proceeding development of light emitting devices (hereinafter referred to as EL light emitting devices) using self-light emitting elements (hereinafter referred to as EL elements) to which EL phenomenon of luminescent materials is applied. The EL light emitting devices, being display devices using self-light emitting elements, necessitate no back-lighting as in liquid crystal display devices. Furthermore, with their wide viewing angles, the EL light emitting devices attract attention for being used as displays of portable units used outdoors.
There are two types of the EL light emitting device, i.e. an active matrix type and a passive matrix type there has been development of both types actively carried out. At present, the active matrix type EL light emitting device is particularly noted. The active matrix type EL light emitting device is characterized in that a thin film transistor (hereinafter referred to as TFT) is provided for each of pixels of a pixel section to control an amount of current flowing in an EL element.
The advantage of the active matrix type is that a highly fine image can be displayed and an image with larger amount of information can be provided.
However, it makes a manufacturing process complicated to provide the TFT for each of the pixels, and there are caused problems of reduction in yield and increase in manufacturing cost due to a protracted manufacturing term. In particular, many photolithography steps cause remarkable reduction in yield, and reduction in number of photolithography steps was an important subject.
In view of the above-mentioned problem, it is an object of the present invention to provide an inexpensive light emitting device and a manufacturing method thereof, for which the number of photolithography steps is reduced for improving yield and shortening manufacturing term to reduce manufacturing cost. In addition, it is another object of the present invention to provide an inexpensive electronic appliance for which an inexpensive light emitting device is used as a display.
In order to achieve the above objects, the light emitting device according to the present invention is characterized with a gate electrode comprising a plurality of layers each with a different kind of conductive film, and the conductive films with respectively different thicknesses are provided by making use of their selectivity in etching and are used as masks for adjusting concentrations of impurity regions formed in an active layer. The above reduces the number of photolithography steps in relation to manufacturing the TFT for improving yield of the light emitting device and shortening manufacturing term thereof.
A typical manufacturing process of an n-channel TFT which characterizes the present invention will be explained with reference to FIGS. 1A through 1E. In FIG. 1A, reference numeral denotes an insulator 100, which is a substrate provided with an insulating film thereon, an insulating substrate, or an insulating film. On the insulator 100, there is formed a semiconductor film (typically a silicon film) 101 which becomes an active layer of the TFT. The semiconductor film 101 is covered with an insulating film 102 containing silicon, which film becomes a gate insulating film of the TFT. For the insulating film containing silicon, silicon oxide film, silicon nitride film, silicon oxynitride film, or a laminated film of combination of them can be used.
Next, on the insulating film 102 containing silicon, there is formed a first conductive film 103 and a second conductive film 104. Here, it is important that the first conductive film 103 and the second conductive film 104 are allowed to have selectivity to each other in etching. Specifically, it can be said that it is important that there is an etching condition under which the second conductive film 104 can be etched with the first conductive film 103 being left.
Typical combination of the first conductive film 103 and the second conductive film 104 are listed as 1) the combination of a tantalum nitride film as the first conductive film and a tungsten film as the second conductive film, 2) the combination of a tungsten film as the first conductive film and an aluminum film as the second conductive film, or 3) the combination of a titanium nitride as the first conductive film and a tungsten film as the second conductive film.
In the above combination of 1), the tungsten film and the tantalum nitride film are etched by a combination of chlorine (Cl2) gas and carbon tetrafluoride (CF4) gas. By adding oxygen (O2) gas to the gasses with the combination an etching rate of the tantalum nitride film is extremely reduced to allow to provide selectivity for the conductive films.
Moreover, in the above combination of 2), with the combination of bromine trichloride (BrCl3) gas and chlorine (Cl2) gas, an aluminum film is etched and a tungsten film is not. Furthermore, with the combination of chlorine (Cl2) gas and carbon tetrafluoride (CF4) gas, a tungsten film is eched, but an aluminum film is not. In this way, selectivity can be provided for both of the conductive films.
Next, as shown in FIG. 1B, the first conductive film 103 and the second conductive film 104 are etched by using a resist mask 105 to form a gate electrode 106. Here, a gate electrode obtained by etching the first conductive film is to be referred to as a first gate electrode, and a gate electrode obtained by etching the second conductive film is to be referred to as a second gate electrode. Therefore the gate electrode 106 comprises the first electrode 106a and the second gate electrode 106b. 
The gate electrode 106 is preferably formed in a tapered shape with an etching condition. Being tapered is that an edge face of the electrode has an inclined part with an angle between the edge face and the under film which is referred to as a tapered angle. To be formed in the tapered shape is that the electrode is formed in a shape with edges each being inclined with a tapered angle. A trapezoid is included in a tapered shape.
In forming the gate electrode 106, the gate insulating film 102 is also etched slightly to be a little thinned. The thinning is preferably restrained within 20 to 50 nm although it is differed depending on etching conditions.
In this state, an impurity element (hereinafter referred to as n-type impurity element) is added into the semiconductor film 101 for making the semiconductor an n-type semiconductor. At this time, the gate electrode 106 is used as a mask to add the n-type impurity element to the semiconductor film 101 in being self-aligned. As a specific n-type impurity, an element which belongs to group fifteen in the periodic table (typically phosphorus or arsenic) can be used.
A well-known plasma doping method or an ion implantation method can be used as the method for addition. The impurity element can be added to the semiconductor film in concentrations from 1xc3x971020 to 1xc3x971021 atoms/cm3. Each of regions 107 and 108 with addition of an n-type impurity element in such concentrations is to be referred to as an n-type impurity region (a).
In the next, as shown in FIG. 1C, the gate electrode 106 is further etched under the same condition as that of forming the gate electrode 106. Then a gate electrode 109 is formed with further thinned width (the gate electrode 109 comprises a first gate electrode 109a and a second gate electrode 109b). At this time, there is the progress of thinning of the gate insulating film 102.
While the etching step shown in FIG. 1C is carried out, the etching condition is changed so as to allow the second gate electrode 109b to be selectively etched. Parameters such as the etching gas, substrate bias voltage, and electric power applied to electrodes, may be changed. Here, since it is necessary only to conserve selectivity between the first gate electrode 109a and the second gate electrode 109b, the easiest way therefore is to change the etching gas.
Thus, as shown in FIG. 1D, a gate electrode 111 is formed which comprises the first gate electrode 109a and a second gate electrode 110.
In this state, the doping step with the n-type impurity element is carried out again. The doping step is carried out with a higher acceleration voltage than that in the step shown in FIG. 1B so that the impurity element can reach deep location. At this time, regions denoted by reference numerals 112 and 113 are doped with an n-type impurity element in concentrations from 1xc3x971017 to 1xc3x971019 atoms/cm3. Each of the regions 112 and 113 doped with the n-type impurity element in such concentrations is to be referred to as an n-type impurity region (b).
Moreover, regions denoted by reference numerals 114 and 115 are also doped with the n-type impurity element each through an end portion of the first gate electrode 109a (a portion without being in contact with the second gate electrode 110). Therefore, concentrations of the n-type impurity element in the regions 114 and 115 are lower than those in the n-type impurity region (b) (preferably in from 1xc3x971016 to 5xc3x971018 atoms/cm3). Each of the regions 114 and 115 doped with the n-type impurity element in such concentrations is to be referred to as an n-type impurity region (c).
A region 116 which is not doped with the n-type impurity element is a region which functions as a channel forming region of the TFT, and is formed directly below the gate electrode 110.
Thereafter, as shown in FIG. 1E, a passivation film 117, an interlayer insulating film 118, a source wiring 119 and a drain wiring 120 are formed to complete formation of the n-channel TFT. As the passivation film 117, a silicon nitride film or a silicon oxide nitride film can be used. As the interlayer insulation film 118, an inorganic insulating film, an organic insulating film, or a lamination film of them can be used. A resin film such as polyimide, acrylic resin, polyamide, or BCB (benzocyclobutene) can be used as the organic insulating film. Further, as the source wiring 119 and the drain wiring 120, known conductive films can be used.
In the above manufacturing process, there are only four times of the photolithography steps, which are each carried out when the semiconductor film 101 is formed, the gate electrode 106 is formed, contact holes in the interlayer insulating film are formed, and the source wiring and the drain wiring. In forming a CMOS circuit, an additional photolithography step is required for manufacturing a p-channel TFT. Nevertheless, this requires only five times of the photolithography steps.
The TFT shown in FIG. 1E has the n-type impurity region (b) 113 and the n-type impurity region (c) 115 which are formed between the channel forming region 116 and the drain region 108. Here, the n-type impurity region (c) 115 and the first gate electrode 109a with the gate insulating film 102 therebetween. The structure is very effective in preventing hot carrier deterioration. Moreover, the n-type impurity region (b) 113 is a region with acting like a conventional LDD (light-doped drain).
Therefore, in the TFT shown in FIG. 1E, it is a means for preventing hot carrier to provide the n-type impurity region (c) and it is a means for preventing leak current to provide the n-type impurity region (b). Accordingly the structure with a significantly high reliability is provided. The present invention allows such a highly reliable TFT to be manufactured only with five times photolithography steps. This makes it possible not only to improve yield and shorten the manufacturing term for the whole light emitting device including light emitting elements but also to manufacture an inexpensive and highly reliable light emitting device.